(sponsored by IBM)
(sponsored by Intel)
(Sponsored by Sun Microsystems)
(sponsored by Samsung Electronics)
(sponsored by Veloxsoft)
The LaTTe project started in November, 1997, with funding from IBM T.J. Watson Research Center. Its goal was to develop a high-performance Java virtual machine. LaTTe's high performace stems from the JIT compiler, which compiles a method's bytecode to native machine code when the method is to be executed.
LaTTe's JIT compiler allocates Java stack operands into RISC machine registers very efficiently and does various optimizations on the code, but despite this the JIT compilation overhead is small. Other parts of LaTTe, such as thread synchronization, exception handling, garbage collection, etc. are also optimized for higher performance. LaTTe shows an average of 30% higher performance compared to Sun's JDK 1.2 and JDK 1.3 (Hotspot) in benchmakrs such as SPECjvm98 and the Java Grande benchmarks.
LaTTe is the result of a close collaboration with researchers at IBM T.J. Watson Research Center. We have exchanged research ideas with IBM Watson's Dr. Kemal Ebcioglu and Dr. Erik Altman through video-conferencing every one to two weeks, and have co-authored various papers.
LaTTe's source code was released to the Internet on October, 1999, with a second version having been released. About 1600 copies have been dowloaded at the time of writing.
The IA-64 Itanium processor is Intel's next-generation high-performance 64-bit CPU based on the Explicitly Parallel Instruction Computing (EPIC) architecture. The EPIC architecture, also called the Very Long Instruction Word (VLIW) architecture, is an Instruction Level Parallelism (ILP) architecture where the compiler collects many very simple machine instructions into a single long instruction word, where executing the long instruction word results in the execution of all the simple machine instructions in parallel.
A JIT compiler for an EPIC architecture must not only do register allocation, but also instruction scheduling when compiling bytecode to EPIC instructions. We have already developed such a JIT compilation algorithm for VLIW architectures and will be attempting to apply this to the IA-64. This research will be done in collaboration with a research team, led by Dr. Jesse Fang, at Intel's Microprocessor Research Lab (MRL), with the JIT compiler being implemented on top of the Open Research Platform (ORP) Java virtual machine developed at MRL.
With embedded Java, memory is extremely limited (e.g. digital TVs, mobile phones, smart cards), so that JIT compilers used on desktops cannot be used: "limited" JIT compilers or fast interpreters are better approaches. This project researches performance-boosting technology usable with limited memory, and actually applies these techologies to digital TVs and mobile phones.
This project uses Enhanced Pipeline Scheduling and Selective Scheduling to increase performance of code generated by compilers. We also do technology transfers to Sun by having some members work directly at Sun Microsystems.
CalmRISC is Samsung Electronics' embedded CPU family, and these processors are already being deployed in smart cards, etc. This project develops compilers and a development environment for the CalmRISC, and research is focused on minimizing code size.
We are developing a Java runtime environment for mobile phones, where all phone applications can be written in Java and can be downloaded wirelessly and conveniently.
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